The practice of embedding capacitors in printed wiring boards (PWB) allows for reduced circuit size and improved circuit performance. Capacitors are typically embedded in panels that are stacked and connected by interconnection circuitry, the stack of panels forming a printed wiring board. The stacked panels can be generally referred to as “innerlayer panels.” Embedded capacitors are subject to requirements such as acceptable breakdown voltage, stability of capacitance within specified temperature ranges, low dielectric loss, construction from environmentally acceptable materials, simplicity of manufacture, and amenability to printed circuit board manufacturing techniques. One industry standard, Electrical Industry Association designation X7R, requires that a capacitor's capacitance vary by not more than 15% of its value at 25° C. over a temperature range of 55° C.–125° C. X7R also requires a dissipation factor of less than 2.5%.
The capacitance density of a dielectric is proportional to its permittivity (or dielectric constant K), divided by the thickness of the dielectric. A high capacitance density capacitor can therefore be achieved by using a thin film, high dielectric constant (“high K”) dielectric in the capacitor. High K ferroelectric dielectrics include perovskites of the general formula ABO3, such as crystalline barium titanate (BT), lead zirconate titanate (PZT), lead lanthanum zirconate titanate (PLZT), lead magnesium niobate (PMN) and barium strontium titanate (BST).
A requirement for a high K ABO3 material is the formation of a polar non-centrosymmetric phase. A coherent crystalline dimension in the dielectric must be exceeded in order to form the non-centrosymmetric phase (which is commonly tetragonal, but can be rhombohedral, orthorhombic, or monoclinic). The crystalline dimension is related to macroscopic features such as grain size. In general, grain sizes in excess of 0.1 micron are necessary to develop the high K ferroelectric tetragonal phase in barium titanate (BaTiO3). Most conventional thin film methods produce grain sizes of about one tenth of this value and correspondingly low dielectric constants.
Thin ferroelectric films are commonly deposited on silicon substrates, which must be processed at relatively low temperatures. Amorphous ferroelectric films, however, more effectively crystallize to the desired high K phase when annealed at high temperatures. Therefore, low temperature annealing of thin ferroelectric films on silicon may not fully crystallize the dielectric to the preferred crystallographic form.
Thin ceramic films may also be deposited on base-metal foils, such as copper and nickel foils. Base-metal foils are subject to oxidation, however, and require low oxygen partial pressures during high temperature annealing. The low oxygen partial pressures, however, can result in complications such as high dielectric losses due to reduction of the dielectric material, suppression of dielectric constant due to reactions between the thin film dielectric and the base metal foil, and oxidation of the base metal during annealing or subsequent re-oxygenation processes.
U.S. patent application 20020195612 A1 to Farrell teaches that copper is a preferred substrate due to its ready availability. However, thin film composites having copper substrates often evidence thermal migration and outgassing. Farrell discloses nickel plating the copper foil, but nickel plating adds cost and complexity, and the dielectric constant is low. Additionally, the dielectric (PZT in Farrell) contains lead which is undesirable from an environmental standpoint.
U.S. Pat. No. 6,541,137 to Kingon et al. teaches that a high temperature deposition or high temperature annealing is incompatible with copper in two ways. First, at the high temperatures and oxidizing conditions required to form a ceramic dielectric, copper forms a thin layer of copper oxide at the interface between the ceramic dielectric and the copper. The copper oxide effectively forms an interface layer, which degrades overall device performance and negates the advantages gained by the use of the ceramic dielectric. Second, the reducing atmospheres favored for copper produce excessive defect concentrations and may frustrate crystalline phase formation in the dielectric oxide layer.
J. T. Dawley and P. G. Clem, Appl. Phys. Lett., vol. 81, No. 16, (2002), p. 3028 discloses K values of 980–1500 obtained by annealing a chemical solution deposition (CSD) film of barium strontium titanate (BST) at 900° C. Dawley and Clem postulated that the high K value was obtained by orienting the BST on biaxially textured nickel tapes. Non-oriented BST exhibited K values in the range of 270–420. BST grain sizes were on the order of 30–35 nm for random BST and 40–50 nm for oriented BST.